1. Field of the Invention
The present invention relates to an output circuit including a MOS FET and, more particularly, to an output circuit in which a conductivity type of a diffusion layer connected to an output node is restricted to one of N type or P type.
2. Description of the Related Art
FIG. 1 shows a conventional output circuit for use in, for example, a clocked inverter circuit. Tri-state buffers 1 and 2 shown in FIG. 1 are constituted by, for example, CMOS circuits, with different power supply voltages Vcc1 and Vcc2 respectively being applied to the buffers 1 and 2. Output nodes of the tri-state buffers 1 and 2 are connected to a bus line 3. When the buffers 1 and 2 are constituted by CMOS circuits, P- and N-type diffusion layers are always connected to the output nodes of the CMOS circuits. Therefore, as shown in FIG. 1, a parasitic diode PD is produced between the output node and the power supply Vcc1. If the relationship between the power supply voltages Vcc1 and Vcc2 is expressed as follows, current flows from the power supply Vcc2 to the power supply Vcc1 through the parasitic diode PD.
Vcc1&lt;Vcc2-1V
FIG. 2 shows another conventional output circuit, which includes N-channel MOS transistors N1 and N2 connected to an output node OT1. Since, however, a substrate (e.g., a P well), not shown, serving as a back gate of the MOS transistor N1 is connected to a ground, the threshold voltage vth of the MOS transistor N1 is considerably higher than normal, due to a back gate bias effect. Assuming that a power supply voltage Vcc is 4.5 V and a threshold voltage Vth is 1 V when a high-level signal is output from the output node OT1, the output signal drops by about 1 V, from the power supply voltage Vcc to about 2.5 V, due to the threshold voltage and also to the back gate bias effect. Taking into consideration irregularities in the threshold voltage Vth, the level of the output signal may be lower than the lowest level 2.4 V of an input signal of a TTL (transistor-transistor logic).
To resolve the above drawback, the gate potential of the MOS transistor N1 can be boosted. However, a booster circuit is required for this and the resultant circuit arrangement is complicated. Further, the substrate of the MOS transistor N1 can be connected to the source thereof. Since, however, the substrate is a P type, a parasitic diode is generated between the substrate and the drain (an N-type diffusion layer connected to the power supply Vcc) of the MOS transistor N1, thereby causing the above-described drawback. Consequently, in the conventional output circuit, the substrate of the MOS transistor N1 cannot be connected to the output node OT1.